Integrated circuit devices, such as synchronous dynamic random access memory devices (SDRAMs), utilize synchronous operation to improve device performance. For example, double data rate (DDR) SDRAMs utilize leading and trailing edges of clock signals to facilitate higher data rate operation. When SDRAMs are operated in the DDR mode, important reference signals are typically generated in-sync with rising and falling edges of a clock signal, to efficiently control operation of such devices as input and output buffers. Unfortunately, conventional attempts to detect rising and falling edges of a clock signal or other control signals may be susceptible to errors if changes in device fabrication techniques, processing conditions or signal noise are significant.
Thus, notwithstanding attempts to provide integrated circuits that operate in a synchronous manner, there continues to be a need for integrated circuits having improved synchronization characteristics.